Computer systems are typically made up of one or more central processing units (CPU), memories, and one or more peripheral devices that allow a CPU to control and transmit data to and from various peripheral units such as printers, disk drives, and the like. The use of a communications interface or system bus for coupling separate devices, such as processors, memories and peripherals, of a computer system is well known in the prior art. Typically, computer systems are designed to allow peripheral devices to be plugged into the system bus. By plugging in appropriate peripheral devices, the computer system can be configured to meet the specific needs of the computer user.
To make their computers more attractive to users, most manufacturers have tried to standardize the design of their computer buses. Standardized buses such as ISA, EISA, and PCI are well known in the prior art. As an example of a standardized bus, the Peripheral Component Interconnect (PCI) bus is a high performance 32 or 64 bit bus with multiplexed address, control and data lines. The PCI bus is intended for use as an interconnect mechanism between highly integrated peripheral devices and processor/memory subsystems. The specification for the PCI bus is set forth in the document PCI Local Bus Specification, revision 2.1, October, 1994. This manual is prepared and maintained by the PCI Special Interest Group (PCI-SIG). The PCI-SIG is an organization that is open for membership to all companies in the computer industry.
While the ability to change the configuration of a computer system by plugging in peripheral devices is a useful and desirable feature of a computer system, it can be difficult to have all the peripheral devices plugged in to a computer system work correctly together. Peripheral devices must be configured so that a CPU can uniquely identify each peripheral device. In the prior art, some peripheral devices require that switches be set to configure the peripheral device. Determining the settings necessary to avoid conflicts between devices is difficult. Making the settings correctly, even if correctly known, could also be difficult. Further, previously correct settings might be made incorrect by later additions of new peripheral devices.
To simplify the addition of peripheral devices to a computer system, it is desirable to have computer systems with automatic configuration support, which is sometimes described as plug and play capability. Automatic configuration allows the automatic software detection of configurable peripheral devices in a computer system and the subsequent assignment of system resources to this hardware. No adjustment of switches or jumpers is required and no resource conflicts should exist after the configuration process is performed.
The PCI bus is an example of an architecture that supports automatic configuration. Among the many features that the PCI Specification provides is the use of address spaces which may be accessed via the PCI bus. The PCI Specification also provides for the use of a base address register to define the starting address of these address spaces. Each of the address spaces on a PCI device may be a size that is a power of two bytes. For PCI Memory the address space is typically from four kilobytes, 212, to two gigabytes, 231, in size. This means that from twelve to thirty-one least significant address bits are required to address a byte in the address space. The remaining most significant address bits are used to distinguish one address space from another. These most significant address bits are the base address for the device. The PCI Specification provides that this base address may be programmed by writing the address into the base address register on the device through the PCI bus. The ability to change the base address of a device in a computer system by a host processor allows the computer system to be configured automatically when power is applied.
The PCI Specification provides for three types of base registers, a Memory Base Address Register, an Expansion ROM Base Address Register, and an I/O Base Address Register. The Memory Base Address Register defines the first address of a block of locations in Memory Space where data may be read or written on the PCI device. The Expansion ROM Base Address Register defines the first address of a read-only memory device (Expansion ROM) residing on a PCI add-in board. The Expansion ROM contains code that is executed by the PCI host processor to provide initialization and system boot functions for the PCI add-in board. The I/O Base Address Register defines the first address of a block of locations in I/O Space which can accept input and output operations on the PCI device.
To configure base addresses dynamically, the host processor needs to know the size of the address space associated with the base address. This allows the host processor to identify valid base addresses and then determine what the next available address will be after the base address is set. Typically, a base address register implements writable bits only for the upper address bits that are not used to address locations within the address space associated with the base address. In a typical PCI device, this means that only the upper one to twenty bits of thirty-two PCI address bits in a Memory or Expansion ROM Base Address Register are writable. This characteristic of the base register can be used to determine the size of the address space associated with the base address register.
The startup protocol defined by the PCI Specification illustrates this technique. In a typical startup of a PCI computer system, an architectured process is practiced between the PCI processor and the PCI device. (See, for example, Edward Solari and George Willse, PCI Hardware and Software Architecture and Design, pp. 558, 588, 610, 723-727 (3d ed. 1996)) During this process, the PCI host computer writes a pattern of all ones, x`FFFF FFFF`, or of all ones except for low order zeroes, e.g., x`FFFF F000`, to a base address register. The base register is then read. The number of ones that were actually written establishes the size of the address space associated with the base address register. For example, if the value returned by reading the base address register is x`FFFF 8000` then a thirty-two kilobyte address space is associated with that base address register.
A limitation of the base address register mechanism is that it does not provide for changing the size of the address space required. For example, a peripheral device might use different plug-in ROMs of differing sizes depending upon the application. Or a device might have differing amounts of RAM that should be made available to the host processor depending on the number of peripheral units being controlled by the device. It is also desirable to be able to produce a general purpose circuit that can provide a peripheral device interface, including a base address register, for a wide variety of peripheral devices that have fixed address space requirements but which vary from device to device.
A solution for changing the size of address space in the prior art is the use of an additional register to define the size of the address space. However, it is desirable that the base register with a changeable address space size continue to function identically to a base address register with a fixed address space size so that the host processors do not require modification to interact correctly with base address registers associated with changeable address space sizes.
One solution to the problem of providing a base address register with a changeable address space size is illustrated by the Intel.RTM. i960.RTM. RP Microprocessor. Intel Corporation, i960.RTM. RP Microprocessor User's Manual, pp. 16-35 to 16-39, 16-42 to 16-43 (1st ed. February 1996). There, the use of a Limit Register is disclosed. A value is written to the Limit Register based on the size of the address space. When the writing of a value of x`FFFF FFFF` to the base register is detected, the next read of the base register returns the value contained in the Limit Register rather than the base register contents.
This solution has several limitations which cause improper operation for some host processors. If the host processor writes a value of other than x`FFFF FFFF` the mechanism which returns the Limit Register value is not triggered. Such writes are valid in the PCI Specification. Detecting a write of x`FFFF FFFF` is difficult unless the write is performed as a thirty-two bit wide, double word, write. The PCI Specification permits the use of four 8 bit wide, byte writes, or two 16 bit wide, word writes. The described mechanism only returns the value of the Limit Register on the first read of the base register after writing x`FFFF FFFF`. However, the PCI Specification permits multiple reads of the base register.
A solution is needed that allows an address space size to be changed and provides a base register that responds to writes and reads in the same manner as if the address space size were fixed.